QUARANET — Defense for Space Infrastructure

Overview

Cyber defense that lives inside the satellite.

An operating-system-independent security core that runs directly on a spacecraft's own processor. It uses 10,000-dimensional mathematics to recognize and neutralize attacks in real time on a power budget so small the satellite barely notices it is protected.

Contact Us → See the Proof

<0.25%

CPU overhead

O(1)

Decision cost

2.5%

Bit-flip tolerance

10K-D

HDC vectors

The Threat Surface

The 2022 Viasat attack disabled tens of thousands of terminals across Europe and it never left the ground segment. As the ground hardens, the attack climbs the chain: the spacecraft is the next link.

— Reflecting CISA / ENISA advisories, 2022

◆ Why ground defense fails in orbit

You cannot lift Earth's firewalls into space. Dynamic memory risks fragmentation and lock-up under hard real-time limits. Conventional AI models suffer silent corruption under cosmic radiation, and data-dependent execution paths break hard real-time guarantees. Small quantized networks can run on flight hardware constant-time behaviour and fault-tolerant model memory do not come with them. Orbit demands deterministic, radically efficient mathematics.

Our Position

We are not another software layer.
We are a structural shield built into the hardware.

Vision

To protect humanity's multi-trillion-dollar orbital infrastructure so every future satellite processor carries an autonomous Quaranet Core that neutralizes threats in the vacuum of space, before they ever reach the ground.

Mission

To move cyber defense off the ground station and into the satellite itself achieved without ever compromising the platform's battery, mass, or latency budget.

Architecture Specifications

Engineered for the physics of orbit.

A software-enforced real-time core today, on a clear path to hardware-level parallelism through FPGA co-design. Figures reflect validated targets and current technology readiness.

SPEC 01 / 03

Hardware-Accelerated O(1) Target & Bounded WCET

1 clk · FPGA

The software layer enforces a strict Worst-Case Execution Time proven at ≈ 6,343 cycles (~10.6 µs) for the classify stage on a real ARM Cortex-R5; ~31 µs end-to-end per packet with the model in TCM (static analysis; 64–125 µs behind cache/flash). We target hardware-level parallel O(1) threat analysis via a Zynq FPGA CAM (RTL-verified, single-clock) (Content-Addressable Memory) architecture.

TARGET · FPGA CO-DESIGN

SPEC 02 / 03

Hardware-Software Co-Designed Resiliency

µs recovery

Under radiation-induced bit-flips and processor lock-ups, our zero-heap architecture lets hardware watchdog resets recover system state within microseconds, while Hamming-SECDED scrubbing self-heals bit-flips in the model memory itself resilience designed jointly across silicon and software.

SEU / RADIATION HARDENED

SPEC 03 / 03

Ultra-Low SWaP Profile

<0.25 %

Compared with conventional AI models, Quaranet adds only <0.25% load to the host CPU preserving the satellite's critical battery and energy budget (Size, Weight & Power).

SWaP OPTIMIZED

Empirical Performance & Validation

Measured, not promised.

Measured results from the binary HDC flight classifier (D = 10,000) the exact model running in the Rust core on the project's real fused dataset CICDDoS2019 + ToN-IoT, 1,327,989 packets evaluated on a held-out, class-balanced set of 7,200 packets; the Rust flight core reproduces every verdict bit-for-bit (golden-vector parity).

Confusion MatrixHeld-out · 7,200

Predictions vs. ground truth on real attack telemetry the model never saw during training.

Pred. Threat

Pred. Benign

Threat

0

TRUE POS.

0

FALSE NEG.

Benign

0

FALSE POS.

0

TRUE NEG.

FPR = 4.08% · ACCURACY = 94.19% · ROC-AUC = 0.9911

Classification MetricsTest Set

Balanced threat/benign performance the model is both precise and sensitive.

Accuracy0%

Precision0%

Recall0%

F1-score0%

BINARY HDC · NEAREST-PROTOTYPE · GOLDEN-VERIFIED RUST PARITY

ThroughputMeasured · SiL

Vectors classified per second, single-threaded NumPy on a commodity CPU during validation.

0

VECTORS / SEC

1,327,989-PACKET FUSED CORPUS · 15 FEATURES

The Mathematical & Physical Proof

Performance that follows from the laws of nature.

Quaranet's advantage on constrained orbital hardware is not a software trick. It is a consequence of high-dimensional geometry, information theory, queueing theory, and thermodynamics. Six of the load-bearing proofs are below.

Geometry · Why 10,000-D

High-Dimensional Orthogonality

In a 10,000-dimensional space, two random vectors are almost always near-orthogonal. Their Hamming distance follows a razor-thin Gaussian: 5000 ± 150 at 3σ.

The chance that random space noise resembles a learned threat profile is ≈ 0. Noise and threat are geometrically separated.

Complexity · O(N²) → O(1)

157 Instructions, Not 100 Million

Neural network · matrix multiply0 FLOPs

Quaranet · Boolean XOR~6.3K cyc · 1 clk FPGA

A 64-bit CPU XORs 64 bits per clock cycle. The whole 10,000-bit decision costs a 157 XOR+POPCOUNT blocks ≈ 6,343 cycles on Cortex-R5 (no hardware popcount), and exactly one clock on the FPGA CAM.

Decision cost is constant regardless of load: O(1) at the hardware level.

Particle Physics · SEU

Immune to Radiation Bit-Flips

THRESHOLD 5000

after 250 flips

Information is spread holographically across 10,000 bits. A radiation storm flips 250 of them by the triangle inequality the decision distance shifts by at most 250, still far below the 5000 threshold.

Even with 2.5% of the hardware corrupted, the verdict is unchanged measured: accuracy holds at 94% under a 2.5% bit-flip storm an accelerated margin test orders of magnitude beyond the expected on-orbit load (≲1 upset/day modeled; ~2–3/day measured COTS anchor), each single upset corrected by SECDED.

Queueing Theory · Anti-Jamming

The Buffer Never Overflows

Processor utilisation under DoS flood1.06%

Queue length L_q = ρ² / (1−ρ) ≈ 0

An M/M/1 model with an arrival rate of 1,000 pkt/s against a service rate of 94,600 classify-stage decisions/s (proven Cortex-R5 WCET; ~32,500 pkt/s end-to-end with the model in TCM) gives ρ ≈ 1.06% ≈ 3.1% end-to-end under a 1,000 pkt/s flood an FPGA CAM lifts μ to ~600M/s.

A massive jamming flood feels like a light breeze memory never overflows.

Thermodynamics · Heat

No Thermal Crisis in Vacuum

Conventional AI · 5 W

≈ 322 K

Quaranet · 0.0125 W

≈ 72 K

In vacuum there is no convection a chip can only shed heat by radiation. XOR logic draws negligible current, approaching the Landauer limit of computation.

No heatsink, no thermal runaway the temperature barely moves.

Rocket Equation · SWaP

Zero Added Launch Mass

$0

hidden launch cost avoided across a 4,000-satellite constellation

Δm = 0 kg · no extra chip, shield, or heatsink

Every extra kilogram lifted to orbit costs thousands of dollars in fuel. A conventional secure payload adds ≈ 2.5 kg (GPU + shielding + heatsink) per satellite.

Quaranet is a few kilobytes of software on the existing processor zero added mass.

Engineering Evidence · TRL-4.5

See the proof, not the promise.

Cryptography, radiation-grade memory, FPGA co-design, an instruction-level timing proof, and real NASA telemetry measured, reproducible, and yours to inspect.

AES-256-GCMSECDED self-heal 1-clock FPGA CAM6,343-cyc WCET NASA SMAP/MSLRF anti-jamming self-red-teamed

Explore the evidence →

Interactive · Defense Simulation

Build a satellite. Launch an attack. Watch it survive.

Pick a real radiation-hardened processor, choose an attack vector, and dial up the intensity. The simulation runs the same queueing-theory math from the proofs above live so you can see for yourself why a multi-million-dollar asset stays online when conventional defenses melt down.

1 · Onboard Processor

2 · Attack Vector

3 · Injection Rate

1,000 packets / sec

4 · Protected Asset

Live packet stream → Quaranet shield

Quaranet CoreREADY

CPU load0%

Buffer occupancy0%

Service rate —

Conventional AIREADY

CPU load0%

Buffer occupancy0%

Service rate —

Configure your satellite and press Run Simulation.

Architecture Roadmap

From TRL-4 to flight-ready hardware.

A disciplined path from validated software to hardware-in-the-loop integration.

Phase 01✓ Completed

TRL-4 · Software-in-the-Loop (SiL) Validation

Detection core implemented as operating-system-independent bare-metal software and validated against fused real-world attack datasets; the Rust flight core reproduces the Python model bit-for-bit (golden-vector parity).

Phase 02✓ Completed

TRL-4.5 · Crypto-Auth, Radiation EDAC & RTL Co-Design

AES-256-GCM (CCSDS 355.0-B) frame authentication, Hamming-SECDED self-healing model memory, an ISA-level WCET proof on ARM Cortex-R5, a synthesizable Hamming-CAM verified at RTL (8/8 golden vectors, single-clock latency), and real NASA SMAP/MSL telemetry integrated into validation.

Phase 03 — Current● In Progress

Hardware-in-the-Loop (HiL) on AMD Xilinx Zynq FPGA

Porting the deterministic core to an AMD Xilinx Zynq FPGA with a CAM-based accelerator for true parallel O(1) analysis the milestone this investment round unlocks.

Phase 04 — NextPlanned

TRL-6 · Flight-Representative Demonstration

A radiation-aware FPGA payload demonstrated in a relevant environment, targeting flight-heritage partnerships with satellite OEMs.

Contact Us

Let's talk about defending what's in orbit.

Whether you're a space agency, satellite OEM, defense fund, or deep-tech investor we'd be glad to walk you through the architecture and the science behind it.

◆Technical discussionArchitecture, benchmarks, and the proofs behind them.

◆Partnerships & researchFlight-heritage and FPGA co-design collaboration.

Send us a message

Let's talk about the technologies of the future, not the past.

We are not another software layer. We are a structural shield built into the hardware.